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3.7 *** Hardware Programming

3.7.1 ** Register

Bytewise - with the only exception of PC.CLOCK which is a 32bit register:

PC.CLOCK .L $18000 R/W
$18002 PC.TCTRL W
$18003 PC.IPCWR W
PC.INTR $18021 R/W
PC.TRAK2 $18023 R
$18063 MC.STAT W

The screen mode can be set with MT.DMODE (1/16), but certain properties can only be controlled via the hardware register at $18063, wich is copied to SV.MCSTA:

Bit Usage
1 screen off
3 resolution - 0: MODE 512, 1:MODE 256
7 alternate video-RAM
0, 2, 5, 6 reserved, all 0's, should never be set!

Keyboard and sound generator can be controlled via MT.IPCOM (1/17).

The system clock can be read, set or adjusted by MT.RCLCK (1/19), MT.SCLCK (1/20) and MT.ACLCK (1/21). Equivalently the timing values in seconds can be read from or written the hardware register at $18000 - which will NOT (nor is it necessary, anyway) work with any(?) QDOS/QL emulators.

3.7.2 ** Serial Ports

The explanations found in {2} seem quite useless, but, these ports can be controlled directly, surprisingly easily. An example can be found in "forth_scr" of the F6 Forth system.

SER2 Pin In-/Output 25-Pin 9-Pin SER2 -> Modem 25-Pin
GND 1 1, 7 5 GND 1, 7
TxD 2 Out 2 3 TxD -> RxD 3
RxD 3 In 3 2 RxD -> TxD 2
RTS (QL: DTR) 4 Out 4 7 RTS -> CTS 5
CTS 5 In 5 8 CTS -> RTS 4
DTR (QL: +12V) 6 Out 20 4 DTR -> DSR 6
Connections as defined by CCITT V.24 DEE (EIA RS232, DIN 66020):
25-Pin 9-Pin In/Out Name X = QL Usage Null-Modem
1 - Out X protective ground 1
2 3 Out TxD X sent data 3
3 2 In RxD X received data 2
4 7 Out RTS X: DTR ready to send 5
5 8 In CTS X clear to send (other's RTS) 4
6 6 In DSR other peripheral ready to operate 20
7 5 Out GND X signal ground 7
8 1 In DCD data set carrier detect(ing) - open -
20 4 Out DTR X: +12V ready to operate 6
22 9 In RNG incoming call - open -
CCIT since 1976 does not define Pin 1, any more.

3.7.3 ** Network

Controlled via $18002, $18020, $18022.
No tests were carried out, and no documentation was found.

3.7.4 ** Microdrives

An example for a 100 kcs test signal is supplied in the hardware manual {14}, and some more with {2}.

PC.MCTRL $18020 motor on/off
PC.TDATA $18022 data out
PC.TRAK1 $18022 data in, track 1
PC.TRAK2 $18023 data in, track 2

Register control of the microdrives is a risky task, thus the microdrives should, if direct access is required, be controlled by the QDOS vectors (pointers offset by $4000):

MD.READ $0124 read
MD.WRITE $0126 write (re "lbl_mdwrite" in PiQdsk)
MD.VERIN $0128 verify
MD.SECTR $012A read sector header

3.7.5 ** I.P.C.

Direct register controlling the IPC is not that difficult as the documentations try to tell, it is difficult to explain, though. Thus, if someone really needs to know, pse read the german "PiQ" version, refer to the above mentioned F6-Forth examples or, mail me...

But, it should be kept in mind that direct hardware control won't work with most QL emulators ("QLAY" being the only known exception) or those more recent "advanced" (super-, hyper-, extra-, mega-) QL/QDOS-ish things, the designers of which seem not to care at all, or simply don't know...

Further, MT.IPCOM is a fairly handy and complete means to get the IPC under control. There are several commands, and a special data protocol to watch:

A3 is expected to pointing to the parameter table as explained below, a resultant byte can be returned in D1; D5 and D7 might be corrupted by the trap call. There is no way (other than direct register control) to receive more than eight bits from a command. Thus the remaining ones cannot be used by MT.IPCOM or, otherwise will irrecoverably lock or even crash the system.

The commands:

RESET.CMD 0 software-resetting the IPC, sound generator disabled, SERial ports closed, their buffers invalidated. Ready to receive new data, re-initiated keyboard control.



input state according to bits set in D1:

STAT..KPN 0 keyboard buffer received some input.
STAT..SON 1 sound generator active
STAT..IP1 4 received data in SER1 buffer
STAT..IP2 5 received data in SER1 buffer
STAT..WP 6 MDV write protection disabled
OPS1.CMD 2 open SER1 for reading, input buffer ready to read.
P24 emitting CTS (acknowledgement) of SER1,
P25 emitting DTR of SER2.
the start-bit initiates *INT to receiving, at P20.
OPS2.CMD 3 as OPS1.CMD, for SER2
CLS1.CMD 4 close SER1, preserve buffer.
CLS2.CMD 5 close SER2, preserve buffer.
RDS1.CMD 6 after a status byte:
bit 0..5, %00111111, no. of received bytes
bit 6 SER1 stop bit missing
bit 7 SER2 stop bit missing
RDS2.CMD 7 for SER2 as RDS1.CMD
RDKB.CMD 8 read keyboard input, after four status bits:
RDKB.NO %0111 3 bits no. of received bytes
RDKB.RPT %1000 bit 3 repeated (pressed) key,
12 bits for each keystroke, the 1st 4 bits:
bit 2 SHIFT
bit 3 keyboard buffer overflow
KBDR.CMD 9 KEYROW, P10 - P17 of the IPC scanned,
D0 - D7 returning the key code.
INSO.CMD 10 start the sound generator,
P21 controlling the acoustic transmitter.
KISO.CMD 11 stop the sound generator.
MDRS.CMD 12 set P26 to inverse bit value.
BAUD.CMD 13 set Baud rate (re tables)
T1 clocked with 4 times the Baud rate
RAND.CMD 14 returns a simply calculated random 16bit number
TEST.CMD 15 functionality control, returning the parameter byte unchanged, otherwise the IPC is (partially) out of order.
UQLX returning the one's complement as a means to detecting it's presence in a QDOS compliant manner.

IPC control parameters:

byte content
1 IPC command in the l.s. 4 bits
2 number of passed parameter bytes
3 - 6 number of valid 4-bit groups of each parameter byte
7 ... parameter bytes
end result bytesize, 0, 4 or 8 bits.

16 pairs of two bits in the bytes 3-6 and the two l.s. bits of the final single byte determining which part (nibble, group of four bits) of the parameter bytes, each, are to be read:

00 l.s. four bits
01 none
10 eight bits
11 none

This group of control bits should always be supplied fully specified.


command 9 read keyrow
1 one parameter
4 Bits row no.
8 Bits column bit set in result byte


UK Style Keyboard MGG Keyboard
1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128
0 F4 F1 5 F2 F3 F5 4 7 0 F4 F1 5 F2 F3 F5 4 7
2 [ Z . C B M ; 2 + Y . C B \ M
3 ] LOCK K S F = G ~ 3 LOCK K S F # G
4 L 3 H 1 A P D J 4 L 3 H 1 A P D J
5 9 W I TAB R - Y O 5 9 W I TAB R Z O
6 8 2 6 Q E 0 T U 6 8 2 6 Q E 0 T U
- the cursor symbols might be not displayed as expected, this is a "translation" -
ENTER left up right down
command 10 use sound generator
8 parameters
8 Bits 1st pitch
8 Bits 2nd pitch
16 Bits pitch1 to pich2 timing
16 Bits duration
4 Bits pitch1 to pitch2 stepping
4 Bits no. of loops
4 Bits stepping width span
4 Bits stepping width span random variation
no result byte
command 11 sound generator off
no parameter
no answer.

3.7.6 ** System Variables


3.7.7 ** Peripheral Extensions

Extension ROM

The ROM slot's address space is $0C000 to $FFFF, for reading, only.
Up to 16 more 16K sections of ROM extensions can be addressed immediately below (SV.RAMT).

After being RESET, when starting, the system scans those addresses for a ROM header at $C000, RAMTOP, RAMTOP-16K, ... RAMTOP-15*16K, and in MINERVA also at $10000 and $14000, the latter of which can also be used with any other QDOS ROM, but will not be scanned.

The ROM-Header:

$4AFB0001 flag presence of an extension ROM
$xxxx zero or ptr w.r.t. header base address, pointing to a BP.INIT table.
$xxxx zero or ptr to initializing routine, which must not change A6 and should restore A0 and A3 on return. 128 bytes of stack memory available.
$xxxx length.w, max 36, of
$x.. an identifying LF (ASCII 10) terminated string.

Extension ROMs at high address space should be programmed relocatibly because the system will allocate them at non-predeterminable addresses.

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